RISC-V, a new chip architecture, is making its way in the tech world. Find out more about its background and how it’s supported in FreeBSD in this article.
I’d very much like me some open source hardware. On a related note, this is an interesting write up on what makes M1 so fast, and in large part it comes down to using a RISC instruction set. Since all the instructions are the same length, it’s possible to process them in batches, and efficiently identify what instructions have inter-dependencies and what don’t. This means you can process independent instructions in parallel. On the other hand, CISC architecture precludes doing this because you can’t efficiently preprocess the instructions to figure out what ones can be parallelized.
I’d very much like me some open source hardware. On a related note, this is an interesting write up on what makes M1 so fast, and in large part it comes down to using a RISC instruction set. Since all the instructions are the same length, it’s possible to process them in batches, and efficiently identify what instructions have inter-dependencies and what don’t. This means you can process independent instructions in parallel. On the other hand, CISC architecture precludes doing this because you can’t efficiently preprocess the instructions to figure out what ones can be parallelized.
Thank you for the info!