This month we reveal that we are working on a powerful and affordable RISC-V single board computer, discuss PineNote’s huge software improvements and provide updates on PinePhone…
Other than being open source which others have already mentioned, the RISC-V instruction set is very optimized, having been developed with the full hindsight of every ISA that came before it as well as being designed for the capabilities of modern silicon, RISC-V cores have the potential to be a lot more efficient than any of the existing dominant ISAs.
Hmm, can’t claim to be an expert, but I heard the opposite. According to the article I read the original RISC-V ISA was developed by the University of California to be simple and easy to teach, but the opposite of optimized.
By now this has surely improved a lot, but most commercially available SoCs seem to include a lot of complex out of spec and proprietary extensions to get semi decent speed. And those larger Chinese server chip designs might be ok for highly parallel workloads, but are not exactly great either (like those old AMD Bulldozer chips).
Other than being open source which others have already mentioned, the RISC-V instruction set is very optimized, having been developed with the full hindsight of every ISA that came before it as well as being designed for the capabilities of modern silicon, RISC-V cores have the potential to be a lot more efficient than any of the existing dominant ISAs.
Hmm, can’t claim to be an expert, but I heard the opposite. According to the article I read the original RISC-V ISA was developed by the University of California to be simple and easy to teach, but the opposite of optimized.
By now this has surely improved a lot, but most commercially available SoCs seem to include a lot of complex out of spec and proprietary extensions to get semi decent speed. And those larger Chinese server chip designs might be ok for highly parallel workloads, but are not exactly great either (like those old AMD Bulldozer chips).